ZILOG Z80 PIO USER’S MANUAL 1.0 INTRODUCTION
The Z8O Parallel I/O (PlO) Circuit is a programmable, two port device which provides a TTL
compatible interface between peripheral devices and the Z80-GPU. The CPU can configure
the Z8O-PIO to interface with a wide range of peripheral devices with no other external
logic required, Typical peripheral devices that are fully compatible with the Z80-PIO include
most keyboards, paper tape readers and punches, printers, PROM programmers, etc. The
Z8O-PIO is packaged in a 40-pin DIP, or a 44-pin PLCC, or a 44-pin OFP. NMOS and
CMOS versions are also available. Major features of the Z80-PlO include.
One of the unique features of the Z80-PlO that separates it from other interface controllers is that all data transfer between the peripheral device and the CPU is accomplished under total interrupt control. The interrupt logic of the PIO permits full usage of the efficient
interrupt capabilities of the Z80-CPU during I/0 transfers. All logic necessary to implement a
fully nested interrupt structure is included in the PIO so that additional circuits are not
required. Another unique feature of the PlO is that it can be programmed to interrupt the
CPU on the occurrence of specified status conditions in the peripheral device. For example,
the PlO can be programmed to interrupt if any specified peripheral alarm conditions should
occur. This interrupt capability reduces the amount of time that the processor must spend in
polling peripheral status.
FEATURES
· Two Independent 8-Bit Bidirectional Peripheral interface Ports with >Handshake=
Data Transfer Control.
· Interrupt Driven ‘Handshake’ for Fast Response.
· Any One of Four Distinct Modes of Operation May be Selected for a Port
including.
- Byte Output
- Byte Input
- Byte Bidirectional Bus (Available on Port A Only)
- Bit Control Mode.
All with Interrupt Controlled Handshake
· Daisy Chain Priority Interrupt Logic included to Provide for Automatic interrupt
Vectoring Without External Logic.
· Eight Outputs are Capable of Driving Darlington Transistors
· All Inputs and Outputs Fully TTL Compatible
· Single 5V Supply and Single Phase Clock are Required
ZILOG Z80 PIO
PIN DESCRIPTION
A diagram of the Z8O-PIO pin configuration is shown in Figure 3-1. This section describes the
function of each pin.
D7 - DO Z80-CPU Data Bus (bidirectional, tri-state) This bus is used to transfer all data and
commands between the Z80-CPU and the Z80-PIO. DO is the least significant bit of the bus.
B/A Sel Port B or A Select (input, active High). This pin defines which port will be accessed during a
data transfer between The Z80-CPU and the Z8O-PIO. A Low level on this pin selects Port A while a
High level selects Port B. Often, Address bit A0 from the CPU will be used for this selection function.
C/D Sel Control or data Select (input, active High). This pin defines the type of data transfer to be
performed between the CPU and the PlO. A High level on this pin during a CPU write to the PIO
causes the Z80 data bus to be interpreted as a command for the port selected by the B/A Select line.
A Low level on this pin means that the Z80 data bus is being used to transfer data between the CPU
and the PlO Often Address bit Al from the CPU will be used for this function.
/CE Chip Enable (input, active Low). A Low level on this pin enables the PIO accept command or
data inputs from the CPU during a write cycle or to transmit data to the CPU during a read cycle. This
signal is generally a decode of four I/O port numbers that encompass Ports A and B, data, and
control.
F System Clock (input). The Z80-PIO uses the standard Z80 system clock to synchronize certain
signals internally. This is a single phase clock.
/M1 Machine Cycle One Signal from CPU (input, active Low). This signal from the CPU is used as a
sync pulse to control several internal PIO operations. When /M1 is active and the /RD signal is
active, the Z80-CPU is fetching an instruction from memory. Conversely, when /M1 is active and
/IORQ is active, the CPU is acknowledging an interrupt. In addition, the /Ml signal has two other
functions within the Z80-PIO.
1. /M1 synchronizes the PIO interrupt logic.
2. When /M1 occurs with out an active /RD or /IORQ signal, the PIO logic enters
a reset state.
/IORQ Input/Output Request from Z80-CPU (input, active Low). The /IORQ signal is used in
conjunction with the B/A Select, C/D Select, ICE, and /RD signals to transfer commands and data
between the Z80-CPU and the Z80-PlO. When /CE, /RD, and /IORQ are active, the port addressed
by B/A will transfer data to the CPU (a read operation). Conversely, when /CE and /IORQ are active
but /RD is not active, then the port addressed by B/A will be written into from the CPU with either
data or control information as specified by the C/D Select signal. Also, if /IORQ and /M1 are active
simultaneously, the CPU is acknowledging an interrupt and the interrupting port will automatically
place its interrupt vector on the CPU data bus if it is the highest priority device requesting an interrupt.
/RD Reed Cycle Status from the Z80-CPU (input, active Low). It /RD is active a MEMORY READ or
I/O READ operation is in progress. The /RD signal is used with A/B Select, C/D Select, /CE and
/IORQ signals to transfer data from the Z80-PIO to the Z80-CPU.
IEl Interrupt Enable In (lnput, active High). This signal is used to form a priority interrupt daisy chain
when more than one interrupt driven device is being used. A High level on this pin indicates that no
other device of higher priority are being serviced by a CPU interrupt service routine.
IEO Interrupt Enable Out (Output. active High). The IEO signal is the other signal required to form a
daisy chain priority scheme. It is High only if IEI is High and the CPU is not servicing an interrupt
from this PlO. Thus, this signal blocks lower priority devices from interrupting while a higher priority
/INT Interrupt Request (output, open-drain, active Low). When /INT is active, the Z80-PIO is
requesting an interrupt from the Z80-CPU.
A7-AO Port A Bus (bidirectional, tri-state). This 8-bit bus is used to transfer data and/or status or
control information between Port A of the Z80-PIO and a peripheral device. A0 is the least significant
bit of the Port A data bus.
/ASTDB Port A Strobe Pulse from Peripheral Device (input, active Low) The meaning of this signal
depends on the mode of operation selected for Port A as follows:
1. Output mode: The positive edge of this strode is issued by the peripheral to acknowledge the
receipt of data made available by the PlO.
2. Input mode: The strobe is issued by the peripheral to load data from the peripheral into the
Port A input register. Data is loaded into the PIO when this signal is active.
3. Bidirectional mode: When this signal is active data from the Part A output register is gated
onto Port A bidirectional data bus. The positive edge of the strobe acknowledges the receipt
of the data.
4. Control mode: The strobe is inhibited internally.
ARDY Register A Ready (output, active High). The meaning of this signal depends on the mode of
operation selected for Port A as follows:
1. Output mode: This signal goes active to indicate that the Port A output register has been
loaded and the peripheral data bus is stable and ready for transfer to the peripheral device.
2. Input mode: This signal is active when the Port input register is empty and is ready to accept
data from the peripheral device.
3. Bidirectional mode: This signal is active when data is available in the Port A output register
for transfer to the peripheral device. In this mode, data is slot placed on the Port A data bus
unless ASTB is active.
4. Control mode: This signal is disabled and forced to a Low state.
B7- B0 Port B Bus (bidirectional, tri-state). This 8-bit bus is used to transfer data and/or status or
control information between Port B of the PlO and a peripheral device. The Port B data bus is
capable of supplying 1.5 m @ 1.5V to drive Darlington transistors. B0 is the least significant bit of the
bus.
/BSTB Port B Strobe Pulse from Peripheral device (input. active Low). The meaning of this signal is
similar to that at /ASTB with the following exception:
In the Port A bidirectional mode, this signal strobes data from the peripheral device into the Port A
input register.
BRDY Register B Ready (output, active High). The meaning of this signal is similar to that of A
Ready with the following exception:
In the Port A bidirectional mode this signal is High when the Port A input register is empty and ready
to accept data from the peripheral device.
IX. Input/Output
Programming Techniques
Input/output Interrupts
Parallel Word Transfer
Parallel Data Transfer
The illustration below shows the parallel transfer of 8 bits of data from the X Register to the Y Register upon application of an enabling transfer pulse. Clearly, parallel data transfer is faster than serial data transfer, but serial transfer has the advantages of requiring less hardware. These registers are made up of D flip-flops, which can serve as memory locations. The information in the X Register is intact after the transfer to the Y Register, so this process shows a possible scenario for accessing digital information stored in memory.
Series Transfer
Input/Output Scheduling
